1. Field of the Invention
This invention relates to an interface for coupling a radio frequency (RF) processing section to a baseband processing section. More specifically, this invention relates to communicating power control messages from the baseband section to the RF section.
2. Related Art
The worldwide use of wireless devices such as two-way radios, pagers, portable televisions, personal communication system (“PCS”), personal digital assistants (“PDAs”) cellular telephones (also known as “mobile phones”), Bluetooth devices, satellite radio receivers and Satellite Positioning Systems (“SPS”) such as the Global Positioning System (“GPS”), also known as NAVSTAR, is growing at a rapid pace. Current trends are calling for the incorporation of SPS services into a broad range of electronic devices and systems, including PDAs, cellular telephones, portable computers, automobiles, and the like.
At the same time, manufacturers design their devices using very different architectures, spanning a wide variety of processors, frequency references, clock rates, and the like. The manufacturers are also very interested in keeping costs as low as possible while providing as much functionality (including SPS capability) as possible. In particular, architectures which split SPS signal processing between a radio frequency (RF) front end a baseband processing section continue to be popular.
For example, SiRF Technology, Inc. of San Jose, Calif. made popular an SPS chipset that included the GRF1 RF chip and GSP1/LX baseband processing chip. These two devices are described in detail in the SiRFStarg® I GPS Architecture GRF1 and GSP1 data sheets. As shown in FIG. 1, the RF chip 102 communicated data samples to the baseband chip 104 using differential sign signal lines (labeled SIGN), differential magnitude signal lines (labeled MAGNITUDE), a GPS clock signal line (labeled GPSCLK), and an acquisition clock signal line (labeled ACQCLK). The baseband chip 104 could communicate with the RF chip 102 in a limited single purpose fashion, namely, by using automatic gain control (AGC) clock, data, and strobe signal lines (labeled AGCCLK, AGCDATA, and AGCSTRB respectively) to provide AGC data to the RF chip 102.
More recent SPS signal processing chipset solutions include the SiRFStar® IIe (centered around the GRF2i RF chip and GSP2e baseband chip) and SiRFStar® IIt (centered around the GRF2i RF chip and GSP2t baseband chip) solutions. Both retained the multiple signal lines used to communicate data samples from the RF section to the BB section and the unidirectional communication of AGC information from the baseband section to the RF section. However, the BB section communicated AGC information unidirectionally to the RF chip using a single pulse width modulated output that the RF chip sampled. In other words, the SiRFStar® IIe eliminated the multiple signal line AGC communication path in favor of a single output line.
For power control, the RF chip typically included a dedicated power control input, for example, one power control input pin that would enable or disable the majority of the RF chip. Thus, there was little or no ability to exercise detailed control over the power consumed by the RF chip. In other words, when the RF chip was active, so were most of the hardware blocks (e.g., phase locked loops, frequency dividers, digital interface sections, and the like) in the RF chip, whether they were needed at the time or not. As a result, the RF chip would consume greater average power than was otherwise necessary. Particularly when incorporated into a device with limited power reserves, such as a battery operated GPS receiver, excess power consumption was a significant drawback.
Therefore, a need exists to overcome the problems noted above and others previously experienced.